A phase-locked loop (PLL) is widely used in communication systems, multimedia systems, and other applications. A frequency synthesizer, an FM demodulator, a clock recovery circuit, a modem, and a tone decoder are examples of devices that use a PLL.
Typically, a PLL includes a phase-frequency detector (PFD), a charge pump, a loop filter, and a voltage-controlled oscillator (VCO). The PLL generates an up signal and/or a down signal, generates a control voltage for a VCO, and adjusts a frequency of a feedback signal based on a phase difference (and a frequency difference) between an input signal and the feedback signal.
When a PLL is in lock mode, the phase difference (and the frequency difference) between the input signal and the feedback signal is locked. When a PLL is not in lock mode, the phase difference (and the frequency difference) between a reference signal and the feedback signal is unlocked. In lock mode in the prior art, the amount of electric charge charging a capacitor of a loop filter is desired to be substantially same as the amount of electric charge discharging the capacitor of the loop filter such that the control voltage for the VCO remains constant.
In the prior art, when the magnitude of a power supply voltage is changed, the magnitude of the control voltage for the VCO is not changed and may remain constant. In that case, the magnitude of a charging current and the magnitude of a discharging current generated from the charge pump of the PLL differ from each other. Such different charging and discharging currents may cause skew to be generated between the input signal and the feedback signal in the lock mode.